1. Field of the Invention
The present invention relates to an electrostatic discharge protecting circuit in a semiconductor device, and more particularly to an electrostatic discharge protecting circuit capable of protecting an internal circuit in a semiconductor device, by minimizing the occupying area thereof.
2. Brief Description of Related Arts
In general, an electrostatic discharge protecting circuit has been widely used to prevent overvoltage from being applied to the internal circuit in the semiconductor device. FIG. 1 is a schematic view illustrating the configuration of a conventional electrostatic discharge protecting circuit. As shown in FIG. 1, the conventional electrostatic discharge (referred to herein as an ESD) protecting circuit is connected to an input/output (I/O) pad which is formed between the ground voltage level Vdd and the power supply Vss in the semiconductor device. To discharge overcurrent from an external circuit, the ESD protection circuit has three current discharging paths provided by a P+/N-well diode 18 and N+/P-well diodes 20 and 22. The first and second current discharging paths are provided by the P+/N-well diode 18 and the N+/P-well diode 20, respectively. The P+/N-well diode 18 is formed between the power supply Vdd and the I/O pad, and the N+/P-well diode 20 is formed between the I/O pad and the ground voltage level Vss. Also, the third current discharging path is provided by the N+/P-well diode 22 formed between the power supply Vdd and the ground voltage level Vss.
FIG. 2 is a sectional view illustrating the detailed structure of the ESD protecting circuit shown in FIG. 1. As shown in FIG. 2, the conventional ESD protection circuit includes a plurality of P-well regions 26, 32 and 34, which are formed by implanting P-type impurity ions into a semiconductor substrate 24, a plurality of N-well regions 28 and 30, which are formed by implanting N-type impurity ions into the semiconductor substrate 24, and a plurality of field oxide layers 360 to 371 spaced apart from one another in order to define active and non-active regions in the semiconductor device 24. Further, the conventional ESD protection circuit includes P+-type impurity regions 381 to 386 and N+-type impurity regions 401 to 405 which are formed between the field oxide layers 360 to 371, respectively. The concentration of the P+-type impurity regions 381 to 386 is higher than that of the P-well regions 26, 32 and 34 and also the concentration of the N+-type impurity regions 401 to 405 is higher than that of the N-well regions 28 and 30.
The P+-type impurity regions 381, 382 and 384 to 386 formed in the P-well regions 26, 32 and 34 are connected to the ground voltage level Vss, and the N+-type impurity regions 402 to 404 formed in the N-well regions 28 and 30 are connected to the voltage supply Vdd. Furthermore, one of N+-type impurity regions 401 and 405 in the P-well regions 26 and 34, for example, the N+-type impurity region 401 and the P+-type impurity region 383 formed in the N-well region 30 are connected to the I/O pad. On the other hand, the N+-type impurity region 405 in the P-well region 34 are connected to the power supply Vdd.
As described above, between the I/O pad and the power supply Vdd, the first current discharging path is formed by the P+/N-well diode due to the junction of the P+-type impurity region 383 and the N-well region 30. The second current discharging path, between the I/O pad and the ground voltage level Vss, is formed by the N+/P-well diode due to the junction of the N+-type impurity region 401 and the P-well region 26, and, between the ground voltage level Vss and the power supply Vdd, the third current discharging path is formed by the N+/P-well diode due to the junction of the N+-type impurity region 405 and the P-well region 34.
However, because the conventional ESD protecting circuit has a plurality of well regions forming the current discharging paths, it has problems in that the lay-out is very complicated and it is in need of a large area in the semiconductor device.